1. Field of the Invention
The present invention relates to semiconductor memory devices, and more specifically, to a semiconductor memory device having a hierarchical word line structure.
2. Description of the Background Art
Related Art 1
With recent increase in storage capacity of semiconductor memory devices, a semiconductor memory device called a DRAM (a Dynamic Random Access Memory) has an input/output line for data in a hierarchical structure having global and local input/output lines in order to achieve high speed operation. In such DRAM, a noise may be introduced to the global input/output line from a signal line which is arranged adjacent thereto, thereby destroying a data signal on the global input/output line. To avoid such problem, a shield line can be arranged adjacent to the global input/output line.
Related Art 2
A DRAM shown in FIG. 11 has a structure in which two input/output line pairs IOPa and IOPb are arranged adjacent to each other. In the DRAM, to column selection gates CSGA and CSGB are simultaneously activated by one column selection line CSL. Thus, even when a data is externally written to a memory cell MCA, a data signal in a memory cell MCB is temporarily read onto a input/output line pair IOPb and again written to memory cell MCB.
Problem Associated With Related Art 1
If the shield line is arranged adjacent to the global input/output line, a layout area increases.
Problem Associated With Related Art 2
When the data signal is written to memory cell MCA, a strong write signal is supplied for a input/output line pair IOPa by a write driver. The data signal for memory cell MCB which has been read onto a input/output line pair IOPb may be inverted by the write signal. Further, the inverted data signal is again be written to memory cell MCB, thereby destroying data.